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DS1689/DS1693
19 of 36
The wake-up feature is controlled through the wake-up interrupt enable bit in extended Control Register
B (WIE, bank 1, 04BH). Setting WIE to 1 enables the wake-up feature, clearing WIE to 0 disables it.
Similarly, the kickstart feature is controlled through the kickstart interrupt enable bit in Extended Control
Register B (KSE, bank 1, 04BH).
A wake-up sequence occurs as follows: When wake-up is enabled via WIE = 1 while the system is
powered down (no VCC voltage), the clock/calendar monitors the current date for a match condition with
the date alarm register (bank 1, register 049H). In conjunction with the date alarm register, the hours,
minutes, and seconds alarm bytes in the clock/calendar register map (bank 0, registers 05H, 03H, and
01H) are also monitored. As a result, a wake-up occurs at the date and time specified by the date, hours,
minutes, and seconds alarm register values. This additional alarm occurs regardless of the programming
of the AIE bit (bank 0, register B, 0BH). When the match condition occurs, the
PWR pin is automatically
driven low. This output can be used to turn on the main system power supply, which provides VCC
voltage to the DS1689/DS1693 as well as the other major components in the system. Also at this time, the
wake-up flag (WF, bank 1, register 04AH) is set, indicating that a wake-up condition has occurred.
A kickstart sequence occurs when kickstarting is enabled via KSE = 1. While the system is powered
down, the KS input pin is monitored for a low-going transition of minimum pulse width tKSPW. When
such a transition is detected, the
PWR line is pulled low, as it is for a wake-up condition. Also at this
time, the kickstart flag (KF, bank 1, register 04AH) is set, indicating that a kickstart condition has
occurred.
The timing associated with both the wake-up and kickstarting sequences is illustrated in the Wake-
Up/Kickstart Timing Diagram in the Electrical Specifications section of this data sheet. The timing
associated with these functions is divided into 5 intervals, labeled 1–5 on the diagram.
The occurrence of either a kickstart or wake-up condition causes the
PWR pin to be driven low, as
described above. During interval 1, if the supply voltage on the DS1689/DS1693 VCC pin rises above the
3V power-fail level before the power-on timeout period (tPOTO) expires, then PWR remains at the active
low level. If VCC does not rise above the 3V power-fail voltage in this time, then the PWR output pin is
turned off and returns to its high-impedance level. In this event, the
IRQ pin also remains tri-stated. The
interrupt flag bit (either WF or KF) associated with the attempted power-on sequence remains set until
cleared by software during a subsequent system power-on.
If VCC is applied within the timeout period, then the system power-on sequence continues as shown in
intervals 2–5 in the timing diagram. During interval 2,
PWR remains active and IRQ is driven to its active
low level, indicating that either WF or KF was set in initiating the power-on. In the diagram,
KS is
assumed to be pulled up to the VBAUX supply. Also at this time, the PAB bit is automatically cleared to 0
in response to a successful power-on. The
PWR line remains active as long as the PAB remains cleared to
0.
At the beginning of interval 3, the system processor has begun code execution and clears the interrupt
condition of WF and/or KF by writing 0s to both of these control bits. As long as no other interrupt within
the DS1689/DS1693 is pending, the
IRQ line is taken inactive once these bits are reset. Execution of the
application software can proceed. During this time, both the wake-up and kickstart functions can be used
to generate status and interrupts. WF is set in response to a date, hours, and minutes match condition. KF
is set in response to a low-going transition on
KS. If the associated interrupt enable bit is set (WIE and/or
KSE), then the
IRQ line is driven active low in response to enabled event. In addition, the other possible
interrupt sources within the DS1689/DS1693 can cause
IRQ to be driven low. While system power is
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